Digital ASIC Designer in Radiation-Tolerant Microcontroller Systems

CERN’s EP-ESE-ME section is seeking a Digital ASIC Designer to develop a radiation-tolerant microcontroller ASIC for future particle physics detectors and accelerator systems. The role involves contributing to the full development cycle, from requirements definition and system architecture to implementation, verification, and post-silicon validation. The project leverages an open-source RISC-V processing core and the CERN SOCRATES framework for fault-tolerant SoC design. Key responsibilities include defining technical specifications, designing and validating the ASIC in 65 nm or 28 nm CMOS technology, integrating peripheral IP blocks, applying fault-tolerant methodologies, and participating in post-silicon testing and characterization. Candidates should have a strong background in digital logic design, RTL development (Verilog/SystemVerilog), ASIC design flows, RISC-V architecture, and embedded systems development with firmware programming in C.